Abstract

In this study, we successfully removed double-slope nonidealities in C60 OFETs by reversing source-gate voltage bias. After a device showed double-slope behavior in Id-Vg scans, a voltage bias was applied between the source and drain electrodes, with its direction opposite from what occurred in the aforementioned Id-Vg scans. A millisecond-long bias pulse was sufficient to change double-slope behavior to near-ideal single-slope performance; additionally, the mobility after the erase was close to the after-kink mobility before bias application. Source-gate voltage scans revealed that after the reversed bias reached 15~20 V, source-drain current witnessed a 100-fold increment. Furthermore, the contact resistance was found lowered in low gate voltages after the bias reversal. We concluded that the bias reversal flushed trapped carriers into the channel, easing transport at low gate voltages by lowering interfacial barriers.

Figure 1: Steps to erase double-slope behavior: 1. Perform the normal Id-Vg scan; 2. Apply a voltage bias between source and drain, with its direction opposite from that in the previous scan; 3. Perform Id-Vg scan again to see the result.